I understand the fundamentals of verilog, but test bench just won't make sense

I understand the fundamentals of verilog, but test bench just won't make
sense

//Half Adder
module half_add(a,b,sum, carry);
input a,b;
output sum, carry;
wire sum, carry;
and(sum,a,b);
xor(carry,a,b);
//begin testbench
initial begin
#100 $finish;
end
initial begin
#10 a = 0; b= 0;
#10 b = 1;
#10 a = 1;
#10 b = 0;
end
endmodule
I am getting illegal assignment errors where I have my time delays and
input assignments...I have seen a few tutorials and I'm using modelsim,
but this just doesn't seem to make sense for me :(. My professor hardly
even went over this.